
use crate::metadata::ir::*;
pub(crate) static REGISTERS: IR = IR {
    blocks: &[
        Block {
            name: "Cryp",
            extends: None,
            description: Some("Cryptographic processor."),
            items: &[
                BlockItem {
                    name: "cr",
                    description: Some("control register."),
                    array: None,
                    byte_offset: 0x0,
                    inner: BlockItemInner::Register(Register {
                        access: Access::ReadWrite,
                        bit_size: 32,
                        fieldset: Some("Cr"),
                    }),
                },
                BlockItem {
                    name: "sr",
                    description: Some("status register."),
                    array: None,
                    byte_offset: 0x4,
                    inner: BlockItemInner::Register(Register {
                        access: Access::Read,
                        bit_size: 32,
                        fieldset: Some("Sr"),
                    }),
                },
                BlockItem {
                    name: "din",
                    description: Some("data input register."),
                    array: None,
                    byte_offset: 0x8,
                    inner: BlockItemInner::Register(Register {
                        access: Access::ReadWrite,
                        bit_size: 32,
                        fieldset: None,
                    }),
                },
                BlockItem {
                    name: "dout",
                    description: Some("data output register."),
                    array: None,
                    byte_offset: 0xc,
                    inner: BlockItemInner::Register(Register {
                        access: Access::Read,
                        bit_size: 32,
                        fieldset: None,
                    }),
                },
                BlockItem {
                    name: "dmacr",
                    description: Some("DMA control register."),
                    array: None,
                    byte_offset: 0x10,
                    inner: BlockItemInner::Register(Register {
                        access: Access::ReadWrite,
                        bit_size: 32,
                        fieldset: Some("Dmacr"),
                    }),
                },
                BlockItem {
                    name: "imscr",
                    description: Some("interrupt mask set/clear register."),
                    array: None,
                    byte_offset: 0x14,
                    inner: BlockItemInner::Register(Register {
                        access: Access::ReadWrite,
                        bit_size: 32,
                        fieldset: Some("Imscr"),
                    }),
                },
                BlockItem {
                    name: "risr",
                    description: Some("raw interrupt status register."),
                    array: None,
                    byte_offset: 0x18,
                    inner: BlockItemInner::Register(Register {
                        access: Access::Read,
                        bit_size: 32,
                        fieldset: Some("Risr"),
                    }),
                },
                BlockItem {
                    name: "misr",
                    description: Some("masked interrupt status register."),
                    array: None,
                    byte_offset: 0x1c,
                    inner: BlockItemInner::Register(Register {
                        access: Access::Read,
                        bit_size: 32,
                        fieldset: Some("Misr"),
                    }),
                },
                BlockItem {
                    name: "key",
                    description: Some("Cluster KEY%s, containing K?LR, K?RR."),
                    array: Some(Array::Regular(RegularArray { len: 4, stride: 8 })),
                    byte_offset: 0x20,
                    inner: BlockItemInner::Block(BlockItemBlock { block: "Key" }),
                },
                BlockItem {
                    name: "init",
                    description: Some("Cluster INIT%s, containing IV?LR, IV?RR."),
                    array: Some(Array::Regular(RegularArray { len: 2, stride: 8 })),
                    byte_offset: 0x40,
                    inner: BlockItemInner::Block(BlockItemBlock { block: "Init" }),
                },
            ],
        },
        Block {
            name: "Init",
            extends: None,
            description: Some("Cluster INIT%s, containing IV?LR, IV?RR."),
            items: &[
                BlockItem {
                    name: "ivlr",
                    description: Some("initialization vector registers."),
                    array: None,
                    byte_offset: 0x0,
                    inner: BlockItemInner::Register(Register {
                        access: Access::ReadWrite,
                        bit_size: 32,
                        fieldset: None,
                    }),
                },
                BlockItem {
                    name: "ivrr",
                    description: Some("initialization vector registers."),
                    array: None,
                    byte_offset: 0x4,
                    inner: BlockItemInner::Register(Register {
                        access: Access::ReadWrite,
                        bit_size: 32,
                        fieldset: None,
                    }),
                },
            ],
        },
        Block {
            name: "Key",
            extends: None,
            description: Some("Cluster KEY%s, containing K?LR, K?RR."),
            items: &[
                BlockItem {
                    name: "klr",
                    description: Some("key registers."),
                    array: None,
                    byte_offset: 0x0,
                    inner: BlockItemInner::Register(Register {
                        access: Access::Write,
                        bit_size: 32,
                        fieldset: None,
                    }),
                },
                BlockItem {
                    name: "krr",
                    description: Some("key registers."),
                    array: None,
                    byte_offset: 0x4,
                    inner: BlockItemInner::Register(Register {
                        access: Access::Write,
                        bit_size: 32,
                        fieldset: None,
                    }),
                },
            ],
        },
    ],
    fieldsets: &[
        FieldSet {
            name: "Cr",
            extends: None,
            description: Some("control register."),
            bit_size: 32,
            fields: &[
                Field {
                    name: "algodir",
                    description: Some("Algorithm direction."),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "algomode",
                    description: Some("Algorithm mode."),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 3,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "datatype",
                    description: Some("Data type selection."),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
                    bit_size: 2,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "keysize",
                    description: Some("Key size selection (AES mode only)."),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 2,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "fflush",
                    description: Some("FIFO flush."),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "crypen",
                    description: Some("Cryptographic processor enable."),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 15 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Dmacr",
            extends: None,
            description: Some("DMA control register."),
            bit_size: 32,
            fields: &[
                Field {
                    name: "dien",
                    description: Some("DMA input enable."),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "doen",
                    description: Some("DMA output enable."),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Imscr",
            extends: None,
            description: Some("interrupt mask set/clear register."),
            bit_size: 32,
            fields: &[
                Field {
                    name: "inim",
                    description: Some("Input FIFO service interrupt mask."),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "outim",
                    description: Some("Output FIFO service interrupt mask."),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Misr",
            extends: None,
            description: Some("masked interrupt status register."),
            bit_size: 32,
            fields: &[
                Field {
                    name: "inmis",
                    description: Some("Input FIFO service masked interrupt status."),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "outmis",
                    description: Some("Output FIFO service masked interrupt status."),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Risr",
            extends: None,
            description: Some("raw interrupt status register."),
            bit_size: 32,
            fields: &[
                Field {
                    name: "inris",
                    description: Some("Input FIFO service raw interrupt status."),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "outris",
                    description: Some("Output FIFO service raw interrupt status."),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Sr",
            extends: None,
            description: Some("status register."),
            bit_size: 32,
            fields: &[
                Field {
                    name: "ifem",
                    description: Some("Input FIFO empty."),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "ifnf",
                    description: Some("Input FIFO not full."),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "ofne",
                    description: Some("Output FIFO not empty."),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "offu",
                    description: Some("Output FIFO full."),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "busy",
                    description: Some("Busy bit."),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
    ],
    enums: &[],
};
